Recently, the level of integration of semiconductor IC chips has progressively risen, techniques for device miniaturization have advanced and abilities of electronic equipment have been enhanced, and the miniaturization of semiconductor IC chips is the trend of the times. As represented by the development of ASICs, further increase in the number of components per chip and further improvement in performance are desired.
Activities for the development of plastic packages employing a lead frame trend from those for the development of surface-mount packages, such as SOJ packages (small outline J-leaded packages) and QFPs (quad flat packages), via those for the development and miniaturization of thin, small plastic packages, such as TSOPs (thin small outline packages) toward those for the development of LOC packages (lead-on-chip packages) to improve packaging efficiency through the three-dimensional arrangement of components in a package.
Further increase in the number of pins, further thickness reduction and further miniaturization have been required of plastic packages in addition to increase in the number of components and functional enhancement. A limit for the miniaturization of the conventional packages has come into view due to restrictions on the arrangement of leads around chips.